The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly relates to a system LSI in which a DRAM is mounted and a method for fabricating the system LSI.
In recent years, there has been an increased demand for high speed processing of a large amount of data such as an image. With an increased data bus width between a memory and a logic in a DRAM embedded LSI in which a DRAM is mounted, the DRAM can perform high speed date processing of a large amount of data. Furthermore, in a DRAM embedded LSI, unlike the case where a memory is externally provided, load-carrying capacitance, load resistance and the like which exist between packages are very small and thus reduction in power consumption is possible. Therefore, it is expected that DRAM embedded LSIs become a solution to the above-described demand.
DRAM embedded LSIs are used for consumer electric appliances centered around AV systems and reduction in cost is highly demanded. Accordingly, how to reduce the area of on-board DRAMs has become a big issue.
FIG. 6 is a plan view illustrating a typical DRAM embedded LSI chip (see, for example, Japanese Laid-Open Publication No. 2003-17582). As shown in FIG. 6, on the DRAM embedded LSI chip, a logic circuit region 101, an analogue circuit region 102, a DRAM core region 103 and an I/O (IN/OUT) circuit region 104 are arranged over a semiconductor substrate 100. In the DRAM core region 103, a control region 105, memory cell array regions 106, sense amplifier regions 107 and a word driver region 108 are arranged. Bonding pad regions 109 are formed in a region of the semiconductor substrate 100 which surrounds the regions 101 through 104, i.e., a peripheral portion of the semiconductor substrate 100. A plurality of MIS transistors having various different driving powers are formed in the regions shown in FIG. 6, respectively.
FIG. 7 is a circuit diagram illustrating a circuit configuration of a typical sense amplifier region in a DRAM embedded LSI. FIG. 7 illustrates a circuit configuration of for the sense amplifier regions 107 in the DRAM embedded LSI of FIG. 6. Although not shown in FIG. 7, the memory cell array regions 106 of FIG. 6 are arranged in both sides of each of the sense amplifier regions 107, respectively.
Each of the sense amplifier regions 107 includes a sense amplifier CIR2 for amplifying a voltage difference between pair bit lines (BITL and XBITL), a switch CIR3 for taking out data from a bit line and a precharge transistor region CIR1.
In the precharge transistor region CIR1, precharge transistors Tr11 and Tr12 for setting the pair bit lines to a precharge potential and an equalizing transistor Tr13 for smoothing a potential between the pair bit lines are arranged. Shared switch transistors Tr14 and Tr15 are arranged so that the shared switch transistors Tr14 and Tr15 are located on the pair bit lines, respectively, between the equalizing transistor Tr13 and the sense amplifier CIR2. By turning ON/OFF the shared switch transistors Tr14 and Tr15, a single sense amplifier CIR2 can be shared by memories arranged on the left and right of the sense amplifier CIR2.
FIG. 8 is a cross-sectional view illustrating respective structures of MIS transistors formed in the regions of FIG. 6 and FIG. 7, respectively. As shown in FIG. 8, for example, an I/O transistor (INPUT/OUTPUT transistor) Tr1, a shared switch transistor Tr2 and a logic transistor Tr3 are formed on the semiconductor substrate 100. The I/O transistor Tr1 is a transistor formed in the I/O circuit region 104 of FIG. 6. The shared switch transistor Tr2 is a transistor formed in each of the sense amplifier regions 107 shown in FIG. 6 and FIG. 7. The logic transistor Tr3 is a transistor formed in the logic circuit region 101, the control region 105 and the like.
The transistors Tr1, Tr2 and Tr3 include gate insulating films 121, 131 and 141, respectively, gate electrodes 122, 132 and 142, respectively, sidewalls 123, 133 and 143, respectively, LDD (lightly doped drain structure) regions 124, 134 and 144, respectively, source/drain regions 125, 135 and 145, respectively, and threshold control layers 126, 136 and 146, respectively.
A thickness of the gate insulating film 131 of the shared switch transistor Tr2 is smaller than a thickness of the gate insulating film 121 of the I/O transistor Tr1 and larger than a thickness of the gate insulating film 141 of the logic transistor Tr3.
The threshold control layer 126 of the I/O transistor Tr1 and the threshold control layer 136 of the shared switch transistor Tr2 are formed by the same ion implantation so as to have the same impurity concentration profile. An impurity concentration of each of the threshold control layer 126 and the threshold control layer 136 is lower than an impurity concentration of the threshold control layer 146 of the logic transistor Tr3.
The LDD region 124 of the I/O transistor Tr1 and the LDD region 134 of the shared switch transistor Tr2 are formed by the same ion implantation so as to have the same impurity concentration profile. A junction depth of each of the LDD regions 124 and 134 is larger than a junction depth of the LDD region 144 of the logic transistor Tr3.